1. Field of the Invention
The present invention relates to a storage control circuit for memory, etc., and more particularly, to a storage circuit for detecting an address-related multi-bit error, and a method of checking errors in the storage control circuit.
2. Description of the Related Art
A storage area in a storage control circuit for memory, etc., is specified with an address to input data to or output it from the storage control circuit. For example, desired data is written to the storage area specified by an address, whereas data is read from the storage area specified by an address.
In general, storage control circuits may develop errors, including those in the form of an address or data value becoming inverted or fixed to 0s or 1s, because of various causes (e.g., noise in a signal line, a faulty buffer used to relay between signal lines, break in a signal line, software error caused by electromagnetic wave). In the event of an address error during data write, for example, data is written to a storage area different from that at the desired address. This may result in the information processing apparatus such as PC (Personal Computer) incorporating the storage control circuit running away out of control.
Likewise, errors in the data to be written may cause the information processing apparatus to run away out of control, and are therefore not desirable. Address or data errors during data read may similarly significantly affect the information processing apparatus incorporating the storage control circuit.
For this reason, error detection techniques have been proposed in the conventional examples. For instance, generation of an error correcting code (ECC) capable of correcting single bit errors and detecting two-bit errors using address information and data stored in a storage device, is described in Japanese Patent Application Laid-Open Publication Nos. 1980-8617, 1978-62936, 1996-235793, 1990-206855 and 1977-2244.
On the other hand, FIG. 1 illustrates an error detection method according to the prior art. FIG. 1 illustrates an example of a storage control circuit operable to generate a check code based on address parity and data, and write the check code to a specified address together with the data.
An address parity check code generation circuit 11 generates an address code 103 based on a parity bit (odd parity as an example in FIG. 1) of an address specified to write data. FIG. 1 illustrates an example of a bit pattern generated by the address parity check code generation circuit 11. The “x” mark indicates those bits that turn ON when the parity bit is 1.
A data check code generation circuit 12 generates a data code 104 based on the data to be written. Although not illustrated, the bit pattern generated by the data check code generation circuit 12 is designed to provide a desired code.
In the case of FIG. 1, the parity bit (odd parity) of a given address 101 (“01010101”) is 1. Therefore, “11111000”, a code having the first five bits set to ON, is generated as the address code 103. The data check code generation circuit 12 generates, for example, “00101001” as the data code 104. Taking the exclusive-OR (EOR) of the two generates a check code 105 (“11010001”), and the check code 105 is written to the storage area specified by the address 101 together with data 102 (“00000001”).
Then, during a data read, a check code is generated from the read data 102 and the address 101 used to read the data as during a data write. The generated check code is compared with the read check code 105. The mismatch between the two codes is detected as an error.
However, the prior arts have the problem that an address multi-bit error may not always be detected. In the conventional example illustrated in FIG. 1, for example, even if two bits are inverted in the address (e.g., if the first and second bits are switched), the parity bit remains 1. As a result, this inversion is not detected as an error.